The present invention relates to an apparatus for controlling I/O interrupts in a multiprocessor system which has a plurality of instruction processors. More specifically, the invention relates to an apparatus for controlling I/O interrupts of a plurality of levels received from a common I/O device, and which selects an instruction processor from the plurality of instruction processors to process each I/O interrupt.
When an I/O interrupt is to be processed in a multiprocessor system which has a plurality of instruction processors, not only the instruction processor which energized the channel that issued the I/O interrupt, but also a desired one of the instruction processors of the plurality of instruction processors is selected, as disclosed in, for example, U.S. Pat. No. 4,271,468. In a system of this type, and I/O interrupt is processed as described below. That is, a request for an I/O interrupt from a channel controller is temporarily stored in a system controller which asks the individual instruction processors whether or not they can accept the interrupt. Each instruction processor informs the system controller whether or not the interrupt can be accepted. When it has received all the replies from the individual instruction processors, the system controller selects the optimum instruction processor, and enables it to perform the interrupt processing. This is described below in detail, with reference to a system constructed as shown in FIG. 1.
FIG. 1 illustrates the construction of a multiprocessor system in which two instruction processors 1A and 1B share a main storage MS3 and a channel controller CHC4 through a system controller SC2. I/O controllers IOC5 are connected to channels CH of the channel controller CHC4, and input/output devices I/O are connected to each of the I/O controllers IOC5. The main storage MS3 stores an interrupt queue 31, which is a list of pending I/O interrupt requests for each of a plurality of levels. in FIG. 1, symbols Q.sub.0 to Q.sub.7 denote queues for each of the levels.
The system controller SC2 is provided with an interrupt-pending register 21 which indicates whether or not the interrupt queues Q.sub.0 to Q.sub.7 in the main storage MS3 are empty, and which has bits 0 to 7 that correspond to the queues Q.sub.0 to Q.sub.7.
An I/O interrupt request is sent from the channel controller CHC4 and is registered in the interrupt queue Qi of the corresponding level in the main storage MS3 by the system controller SC2. In this case, the corresponding bit of the interrupt-pending register 21 in the system controller SC2 becomes "1" when an I/O interrupt request is registered for the first time in an interrupt queue Qi which was empty. When there is already at least one interrupt request, however, that bit is already "1", and the register 21 does not change.
The system controller SC2 sends the contents of the interrupt-pending register 21 to the instruction processors 1A, 1B simultaneously. When the instruction processors 1A, 1B are ready to be interrupted, they send the system controller SC2 IP-accept signals and queue-identifier signals of the highest-order instruction processor which has not been interrupt-masked. In this case, if an instruction processor IP is in a wait state, it also sends a wait signal to the system controller SC2.
The system controller SC2 executes the following processing in response to the signals from the instruction processors 1A, 1B. When the queue-identifier signals from the instruction processors IP do not agree, the instruction processors 1A, 1B perform an interrupt. When the instruction processors 1A, 1B accept the interrupt in response to queue identifier signals of the same level, only one instruction processor IP is selected for the interrupt, according to a predetermined priority. The instruction processor IP which accepted the interrupt but which was not selected sends a reset signal to the system controller SC2 to cancel the accept condition, and returns a latch to its initial condition.
According to the conventional I/O interrupt processing described above, the system controller asks a plurality of instruction processors IP whether or not they can accept an interrupt. When a plurality of instruction processors IP can accept the interrupt, accept signals are sent back from the instruction processors IP to the system controller SC. Therefore instruction processors IP which have sent back accept signals are not able to perform ordinary processing from the time they received the enquiry for interrupt-accept until it is determined whether of not they have been selected. A circuit controlling the interrupt must be provided at two places, i.e., for the system controller SC and for the instruction processors IP, resulting in an increased quantity of hardware, and a complex control operation.